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Espressif Systems /ESP32 /UHCI0 /CONF1

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Interpret as CONF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHECK_SUM_EN)CHECK_SUM_EN 0 (CHECK_SEQ_EN)CHECK_SEQ_EN 0 (CRC_DISABLE)CRC_DISABLE 0 (SAVE_HEAD)SAVE_HEAD 0 (TX_CHECK_SUM_RE)TX_CHECK_SUM_RE 0 (TX_ACK_NUM_RE)TX_ACK_NUM_RE 0 (CHECK_OWNER)CHECK_OWNER 0 (WAIT_SW_START)WAIT_SW_START 0 (SW_START)SW_START 0DMA_INFIFO_FULL_THRS

Fields

CHECK_SUM_EN

Set this bit to enable decoder to check check_sum in packet header.
CHECK_SEQ_EN

Set this bit to enable decoder to check seq num in packet header.
CRC_DISABLE

Set this bit to disable crc calculation.
SAVE_HEAD

Set this bit to save packet header .
TX_CHECK_SUM_RE

Set this bit to enable hardware replace check_sum in packet header automatically.
TX_ACK_NUM_RE

Set this bit to enable hardware replace ack num in packet header automatically.
CHECK_OWNER

Set this bit to check the owner bit in link descriptor.
WAIT_SW_START

Set this bit to enable software way to add packet header.
SW_START

Set this bit to start inserting the packet header.
DMA_INFIFO_FULL_THRS

when data amount in link descriptor’s fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data